As integrated circuits continue to scale downward in size, the finFET (fin type field effect transistor) is becoming an attractive device for use with modern semiconductor devices. In a finFET, the channel is traditionally formed by a semiconductor vertical fin (as compared with a planar channel in a conventional CMOS), and a gate electrode is located and wrapped around the fin. With finFETs, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as so-called Ge, SiGe, or III-V materials, to manufacture FinFET devices, which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation.
One prior art process that has been employed to form alternative fin materials on silicon substrate fins is simply to perform an etch process on a substrate through a patterned hard mask layer to form a plurality of trenches in the substrate. As before, this etching process results in the definition of a plurality of substrate fins. Then, a layer of insulating material is formed in the trenches of the device such that it overfills the trenches. Next, an etching process, such as a dry, wet or vapor phase etching process, is performed to reduce the thickness of the layer of the insulating material, and this process essentially defines the final fin height of the fins. Then, a layer of alternative semiconductor material is formed on the exposed portions of the substrate fins by performing an epitaxial deposition process (referred to as a “cladding” channel formation). Then, a gate structure, either a permanent gate structure or a sacrificial gate structure would be formed on the fins using traditional techniques.
A drawback of the prior art is that the final fin width (initial fin width+twice of the cladding thickness) is too large, such that it limits the scaling of the fin pitch to maximize the channel width under fixed footprint. It is therefore desirable to have improvements in the fabrication of finFETs having a cladding channel.